The present invention relates in general to memory storage and more particularly to a system and method for repairing a memory column.
Virtually any device that utilizes an electronic circuit requires the ability to store information in a memory storage device. Traditional circuit designs may include embedded memories or cache memories. Manufacturing defects occur in the memories due to imperfect processing which results in permanently damaged bits. One approach to repair defective memory bits is a design with an extra redundant memory column/row in the memory array. The defective column/row is found by testing of the wafer. Repair of a defective column/row is performed by replacing the defective column/row with the redundant column/row. This is achieved by reading a data bit from memory into a sensing amplifier and then pass it through a full-swing two input multiplexer. The other input of the multiplexer is redundant. The multiplexer only outputs the data bit received from memory if the memory column/row is not defective. This multiplexer configuration prevents data errors from being communicated to the rest of the circuit. A second approach to error correction involves two data storage arrays. Data is stored in a first array and a second array is filled with redundant data bits. Upon discovering a defective bit in the first array, the redundant bit from the second array may be used to replace the erroneous bit. Both of these approaches, however, consume a large amount of circuit area and circuit power and introduce substantial time delays into the circuit. Therefore, it is desirable to efficiently correct errors in memory devices.
From the foregoing, it may be appreciated by those skilled in the art that a need has arisen for a method of repairing a memory using a low power multiplexer that causes no time delay. In accordance with the present invention a system and method for repairing a memory column is provided that substantially eliminates or greatly reduces disadvantages and problems associated with conventional memory repair techniques.
According to one embodiment of the present invention, there is provided a system and method for repairing a memory column. The system includes a multiplexer operable to receive a first data bit and a second data bit. The multiplexer is operable to select one of the first data bit and the second data bit. The system also includes a control generator operable to receive a control signal indicating an error in the first data bit. The control generator is operable to generate a select signal, and the multiplexer is operable to select the second data bit in response to the select signal.
The present invention provides various technical advantages over conventional memory repair techniques. For example one technical advantage is to replace defective bits in a memory storage device without causing circuit timing delays. Another technical advantage is to prevent errors in data bit storage from being passed throughout a circuit in a space-saving and energy efficient manner. Yet another technical advantage is the ability to perform local bit switching without the need to perform global bit switching in tandem. Other technical advantages may be readily ascertainable by those skilled in the art from the following figures, description, and claims.